AMD Unveils Venice and MI400 SoCs at CES 2026

At CES 2026, AMD lifted the veil on its highly anticipated Venice and MI400 System-on-Chips (SoCs). The presentation provided a comprehensive overview of the architectural roadmap for the coming years. The Venice architecture represents the next generation of AMD's high-performance computing platform, built to succeed the current generation of chips.

Significant attention was given to the manufacturing process nodes. The disclosures confirmed that Venice and MI400 are being fabricated using cutting-edge 3nm and 2nm process technologies from leading foundries. The presentation also detailed the evolution of the Infinity Fabric interconnect and the integration of advanced memory standards. These updates signal AMD's continued aggressive stance in the competitive semiconductor landscape.

The Venice core architecture was the centerpiece of the CES 2026 disclosures. AMD engineers detailed the microarchitectural changes designed to maximize instructions per clock (IPC). The new design features an expanded instruction window and improved branch prediction accuracy. These changes are intended to reduce stalls and increase throughput for complex workloads.

Key improvements in the Venice architecture include:

• An enhanced AVX-512 implementation for higher floating-point throughput.
• Increased L1 and L2 data cache bandwidth to feed the execution units.
• Optimized branch prediction units to minimize pipeline flushes.

The architecture is designed to scale across a wide range of TDPs, from mobile form factors to high-end desktop and server environments. AMD emphasized that Venice maintains compatibility with the existing AM5 socket infrastructure, ensuring a smooth upgrade path for consumers.

Alongside the Venice CPU cores, AMD unveiled the MI400 series of SoCs, which place a heavy emphasis on AI and machine learning capabilities. The MI400 integrates next-generation RDNA graphics cores with dedicated AI accelerators. This heterogeneous design allows the chip to handle graphics rendering and parallel AI computations simultaneously.

The MI400 series introduces a new memory subsystem architecture. AMD announced support for LPDDR6 memory, offering significantly higher bandwidth and lower power consumption compared to previous generations. This is critical for AI workloads that are memory-bandwidth intensive. The integrated Neural Processing Unit (NPU) has been upgraded to deliver up to double the performance of the previous generation, enabling on-device processing for large language models and generative AI applications.

The physical construction of the Venice and MI400 chips highlights AMD's mastery of advanced manufacturing. The chips are being produced on TSMC's N3X and N2P process nodes. These nodes offer substantial gains in transistor density and power efficiency. The use of these advanced nodes allows AMD to pack more cores and cache onto a single die.

AMD also discussed the packaging technologies used for these SoCs. The company is utilizing:

• 2.5D packaging for high-bandwidth interconnects.
• 3D stacking for cache integration.
• Advanced thermal interface materials to manage heat density.

These manufacturing advancements are crucial for maintaining the performance-per-watt leadership that AMD has achieved in recent years. The transition to these nodes is reportedly on schedule for mass production later in the year.

While specific benchmark numbers were not finalized, AMD provided estimated performance uplifts for the Venice and MI400 platforms. In compute-heavy workloads, Venice is projected to offer a 20-25% improvement over the current generation. This gain is attributed to a combination of higher clock speeds and architectural efficiency.

For the MI400 series, the focus is on AI performance. AMD targets a 2x increase in TOPS (Trillions of Operations Per Second) for AI inference tasks. The company also highlighted improvements in power efficiency, aiming to reduce total system power consumption in mobile devices by up to 15% under typical usage scenarios. These projections place the upcoming chips in a strong competitive position against rival offerings from Intel and NVIDIA.